Society for Computer Technology and Research's
PUNE INSTITUTE OF COMPUTER TECHNOLOGY
Department of Computer Engineering
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D to SR Conversion Truth Table
Block Diagram of D FlipFlop
Run Simulation
Inputs
Outputs
Destination FlipFlop
Present State
Next State
S
R
Qn
Qn+1
D
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
0
0
1
0
0
1
1
1
0
1
1
1
1
1
Invalid
X
1
1
Invalid
X